POWER / CAPACITORS / FILTERS
Explore capacitor resonance, budget output capacitance, inspect a loaded LC filter, and adjust a measured loop response.
Explicit small-signal and ideal buck models. Use effective capacitance at operating voltage and temperature, measured or manufacturer ESR/ESL, and your regulator’s stability requirements. This tool does not identify a controller model from a load-step waveform.
Each branch is ESR + jωESL + 1/(jωC); identical parts within a bank are parallel. Different banks combine as complex admittances. Quantities do not include common mounting or plane inductance. ESR/ESL must be positive; ideal lossless singularities are excluded.
Plot: |Z| in Ω on a logarithmic vertical axis. Local maxima can reveal anti-resonance between banks. Extrema use 501 log-spaced samples and can miss a narrow peak; narrow the sweep to inspect it. A lower ESR may make an anti-resonant peak worse.
Ripple sizing assumes an ideal buck in continuous conduction, triangular ripple current and a lumped output capacitor below self-resonance. The ripple estimate adds C and ESR contributions as an engineering budget; it does not reconstruct their exact waveform. Capacitance is effective total C, not the nameplate value.
Transient budget assumes the capacitor supplies the entire specified load-current increase for the entered deficit duration: ΔV ≈ ΔI·t/C + ΔI·ESR + ESL·ΔI/tedge. This combines separate approximate contributions, not an exact transient simulation. The duration is an input assumption, not an inferred loop response. Mixed-bank ESR uses the low-frequency equivalent; ESL uses the high-frequency parallel limit. Shared routing inductance, ringing, load release, saturation and controller recovery are excluded.
D = Vout/Vin; ΔIL = Vout(1−D)/(L·fs); ΔVripple ≈ ΔIL/(8·fs·C) + ΔIL·ESR; IC,rms = ΔIL/√12
Required C is calculated after subtracting ESR (and for the transient, ESL) contributions from the voltage target. If no budget remains, more capacitance alone cannot meet that model’s target. Check capacitor ripple-current ratings, DC bias derating, operating voltage and controller-approved C/ESR ranges separately. Do not choose a part solely from the calculated minimum.
source → (Rseries + Lfilter) → output; output → capacitor bank ∥ Rload → return
Plots: absolute voltage gain in dB and phase in degrees. H(f) = Zshunt / (Rseries + jωLfilter + Zshunt). This is the passive filter transfer from an ideal source, including the capacitor-bank RLC model above. Positive gain identifies modeled peaking. Increasing series resistance can damp the peak but increases DC loss. The nominal ideal LC frequency is only a reference, not the actual peak or −3 dB corner.
An extra output filter can interact with regulator feedback or a constant-power load. This resistive-load model does not determine converter-loop stability, nor include magnetic saturation, inductor self-resonance, distributed geometry or EMI compliance.
Paste an open-loop return-ratio sweep using the negative-feedback convention (unity-gain crossing and phase approaching −180°). Enter strictly increasing frequency in Hz, gain in dB, and unwrapped phase in degrees. No header row. Comments begin with #.
Gray = supplied sweep; accent = adjusted model. The extra transfer is K(1+jf/fz)/(1+jf/fp), with K = 10^(gain_dB/20). Equal zero and pole leave the phase unchanged. A zero below the pole adds phase lead; a pole below the zero adds phase lag.
Crossovers are interpolated in log frequency between the supplied samples; PM = 180° + phase at each 0 dB crossing. No extrapolation, gain-margin claim, or stable/unstable verdict is generated. Multiple crossings, phase wrapping, sparse measurements, delays and right-half-plane poles/zeros require a complete loop/Nyquist review. This is a hypothetical transfer adjustment; actual compensator component values depend on the controller topology and must be remeasured.
The loaded filter and lead/lag calculations follow complex impedance and transfer-function algebra shown here. Numerical checks cover analytic examples and invalid inputs; they do not establish agreement with your hardware.