Interface reference · reviewed November 2026

SerDes links & channel design

SerDes describes serialization and deserialization. It is not one electrical standard, one connector, or one impedance.

Follow the link end to end

TX serializer / driver → package → PCB → connector / cable → PCB → RX / CDR
                  reference clock, power, reset and sideband control
               A full-duplex link normally has separate TX and RX pairs.

Connect TX to the peer’s RX and preserve pair polarity unless both the hardware and protocol support inversion. Lane reversal, lane reordering and polarity inversion are different capabilities. Check each explicitly.

Term	Meaning	Design implication
NRZ	Two signal levels, one bit per symbol.	UI = 1 / bit rate; 10 Gb/s NRZ gives a 100 ps UI.
PAM4	Four levels, two bits per symbol.	Distinguish symbol rate from bit rate; three eyes require their own margins.
Encoding / FEC	Protocol overhead and error handling.	Line rate differs from useful payload rate; do not count encoded bits as payload.
CDR / reference clock	Clock recovery / local clock reference.	Check supported reference-clock architecture, jitter and frequency tolerance.
TX equalization / CTLE / DFE	Transmit and receive channel compensation.	These compensate a channel within limits; they do not remove all loss or reflections.

Architecture: TI LVDS Owner’s Manual, SerDes and jitter chapters. Symbol terminology: IBIS 8.0.

A channel budget needs more than trace length

Track insertion loss, return loss, crosstalk, discontinuities and jitter over the applicable frequency band. A single attenuation number is not an eye diagram. Connector and package models, dielectric/copper loss and via stubs belong in the channel model. Check the receiver’s required BER and eye/compliance criteria using the selected protocol.

For a sampled channel, use the proper port mapping and reference impedance. An S21 magnitude alone says nothing about whether unused ports were correctly terminated.

Equalization and channel settings: Altera link-analysis guide; coupling: TI interface design guide. Endpoint example: AMD transceiver reference-clock requirements.

Routing checklist

Use the transceiver’s differential target and the fabricator’s actual stackup. Solve width/spacing together.
Keep the pair symmetric through pads, breakout and vias; control intra-pair skew.
Preserve the return path at layer changes; keep routing away from plane gaps and noisy supplies.
Minimize unnecessary stubs. Evaluate back-drilling or blind vias from a channel model, not a universal maximum length.
Budget inter-lane skew only where the protocol requires it; do not add long meanders simply to match every lane.
Start bring-up with power/reset/reference clock, then loopback/PRBS and BER diagnostics before full protocol traffic.

PCB geometry: AMD UltraScale transceiver PCB guidance.