Interface reference · reviewed November 2026
LVDS specifies an electrical interface. Data framing, bit order, pixel mapping and clocking still depend on the devices and protocol.
Driver OUT+ ───────────────┬── Receiver IN+
│
Rterm (typically 100 Ω)
│
Driver OUT− ───────────────┴── Receiver IN−
Termination at the receiver; omit if integrated.Classic LVDS has a small differential swing, typically around 350 mV with a common-mode voltage around 1.2 V. Those are orientation values; check output swing and receiver common-mode/input limits at the actual supply and temperature. A 3.3 V supply does not mean a 3.3 V signal swing.
Choose a termination matching the line and receiver requirements. Do not automatically add two 100 Ω resistors. AC coupling requires a compatible data pattern and explicit receiver bias; DC coupling requires compatible common-mode ranges and ground offset.
Levels: TI DS90LV011AH datasheet; coupling and layout: TI LVDS Owner’s Manual. Termination: Analog Devices termination guidance.
| Item | Check |
|---|---|
| Topology | Point-to-point LVDS and multipoint M-LVDS are different electrical cases. Do not create a multidrop bus by copying a point-to-point circuit. |
| Polarity & mapping | Track +/− through both connector drawings. Check serializer lane mapping and display data mapping separately. |
| Clock / data | Determine whether the clock is forwarded or recovered. Check sampling edge, channel-to-channel skew and setup/hold limits. |
| Layout | Use controlled differential impedance, symmetric breakout and continuous return paths. Avoid stubs and unnecessary probing pads. |
| Idle state | Review open/short/undriven receiver behavior. “Failsafe” is a device feature, not a guarantee implied by LVDS. |
| Measurement | Use appropriate differential probing and bandwidth. Inspect differential and common-mode behavior without adding an accidental heavy load. |
Topology, timing and idle behavior: Analog Devices AN-1177: LVDS and M-LVDS implementation.