Interface reference · reviewed November 2026

Ethernet types, connections & layout

Keep three boundaries distinct: the MAC interface, the PHY, and the cable or optical medium.

Which Ethernet?

Physical link	Nominal rate	Medium / distinction
10BASE-T	10 Mb/s	Two twisted pairs; conventional 100 m channel class.
100BASE-TX	100 Mb/s	Two twisted pairs; conventional 100 m channel class.
1000BASE-T	1 Gb/s	Four pairs, bidirectional signaling on each pair; conventional 100 m channel class.
10BASE-T1S / T1L	10 Mb/s	Single-pair families with different topology and reach requirements; not ordinary RJ45 pin-compatible links.
100BASE-T1 / 1000BASE-T1	100 Mb/s / 1 Gb/s	Single-pair PHYs; select the matching coupling network and connector.
Optical Ethernet	Variant-specific	Optical modules and fibers replace the copper MDI path; select the exact optical standard.

Rates describe the link family, not application payload throughput. Cable category, channel construction and the precise PHY standard determine permitted reach.

Families: Microchip Ethernet overview and Microchip single-pair Ethernet.

Connection map

MAC ⇄ MII / RMII / RGMII / SGMII ⇄ PHY ⇄ magnetics ⇄ 8P8C ⇄ cable
                 MDC / MDIO → PHY management
     Copper BASE-T example; not a universal T1 or optical circuit.

MAC–PHY side	What travels on it	Watch for
MII / RMII	Parallel data and control; RMII reduces pin count.	Clock direction, I/O rail and the PHY’s reference-clock mode.
RGMII	4-bit DDR data paths, clocks and control.	Budget transmit and receive clock skew separately. Assign intended delay to the MAC, PHY or PCB and check the combined timing.
SGMII	Serial differential transmit/receive paths.	Lane rate, AC coupling, termination and common-mode requirements from both endpoints.
MDC / MDIO	Management clock / bidirectional register access.	PHY address straps, MDIO pull-up and reset-time strap sampling.

Concrete interface, strap and RGMII-delay examples: TI DP83867 datasheet. Its settings are device-specific.

8P8C contacts: preserve the actual twisted pairs

The contact pairs are 1–2, 3–6, 4–5, 7–8. Pins 3 and 6 belong together even though they are not adjacent. For conventional 10/100 MDI, 1–2 is TX and 3–6 is RX; MDI-X reverses those roles. Gigabit BASE-T uses all four pairs. Auto-MDI-X support does not excuse a split pair.

Confirm connector contact numbers from its drawing; solder-side and mating-side views mirror each other. T568A and T568B are cable color assignments, not alternative PHY pinouts. Use the PHY and magnetics drawings to map PCB nets to cable contacts.

Contact map: Cisco 10/100 Ethernet cable and connector guide.

Layout & bring-up checklist

Use the PHY’s MDI differential-impedance target and length/skew limits; 100 Ω is common for copper MDI.
Check whether termination is internal before adding resistors. Use the specified magnetics, center-tap wiring and common-mode network.
Keep pairs balanced with a continuous reference on the PHY side. Apply the manufacturer’s copper keep-outs under the isolation barrier and magnetics.
Place the PHY clock, bias resistor and decoupling close to their pins; separate noisy switching nodes.
Review ESD paths, shield/chassis connection and isolation spacing as a system. PoE requires its own compliant power interface.
For a dead link: verify rails, reset, clock, straps, MDIO identity, negotiation state and cable pairs before changing RGMII delay.

Layout basis: TI Ethernet PHY PCB checklist; example MDI circuit: TI TIDA-010046 design guide.