Interface reference · reviewed November 2026

DDR timing & routing

A bench-side guide to the timing vocabulary and routing groups. Use the exact controller, DRAM speed grade, package and memory topology to set constraints.

Clock cycles are not nanoseconds

For a double-data-rate data bus, tCK (ns) = 2000 / data rate (MT/s). One data transfer interval is half a clock period. A 3200 MT/s bus has a 0.625 ns clock period; CL22 corresponds to 13.75 ns of CAS latency. This is arithmetic, not total system memory latency.

Term	Meaning	Read it carefully
CL / tAA	Read-command to first data timing	CL counts CK cycles; the part also specifies time limits.
tRCD	ACTIVATE to READ/WRITE delay	Opening a row is separate from reading it.
tRP / tRAS / tRC	Precharge / minimum row-active / row-cycle time	Check each requirement; do not infer a speed bin from the headline MT/s.
tRFC / tREFI	Refresh recovery / refresh interval	Density and operating conditions affect the applicable limits.
tRRD / tFAW	ACTIVATE spacing / four-activate window	Bank-group and power constraints matter.
tDQSQ, setup & hold	Data/strobe relationship and sampling margins	Include controller/DRAM timing, package and PCB skew, jitter and training.

Timing terminology: AMD DRAM timing reference. An example operating point is documented in Intel’s memory timing table.

Route groups, not one giant length-matched bus

Group	Connections	Routing intent
DQ + DM/DBI + DQS pair	Data group associated with its strobe	Match delay within the controller-defined byte/nibble group; preserve DQS pair symmetry.
CK pair	Controller clock to memory	Use the topology, termination and skew budget for the chosen population.
Address, command, control	Shared command path	DDR4 examples use fly-by; do not copy that rule blindly to another generation or topology.
VREF, VTT, supplies	References, termination supply and power	Follow generation-specific sourcing, decoupling and reference-plane guidance.

Match propagation time, including package contributions, rather than copper length alone. Different layers and via transitions introduce different delays. Keep reference planes continuous, transitions consistent and tuning compact. Confirm permitted bit swaps with the memory-controller documentation before changing pin order.

Routing basis: TI AM65x/DRA80xM DDR guidelines, AMD DDR4 connections, AMD DDR4 physical rules, and Altera delay matching guidance.

Before bring-up

Reconcile controller-supported memory, ranks, widths, rails and speed grade.
Extract per-group delay, impedance and via counts from the actual stackup.
Check reset, clock, references and termination before investigating training.
Use the controller’s memory-test and training reports; a successful boot alone does not measure timing margin.

DDR3/4/5 and LPDDR families differ in signaling, channels, training and power requirements. This sheet provides vocabulary and a review sequence, not interchangeable layout constraints.