555 Timer

Astable & Monostable

OPERATING MODE

Resistor 1 (R1)
Resistor 2 (R2)
Capacitor (C1)
Time T
Frequency ($f$)
0.00 Hz
Duty Cycle
0.0 %
Time High ($T_H$) 0.0 ms
Time Low ($T_L$) 0.0 ms

Math & Theory

Ideal 1/3-to-2/3 supply threshold timing: astable tH = ln(2)(R1+R2)C, tL = ln(2)R2C; monostable t = ln(3)R1C. Actual timing depends on IC thresholds, discharge voltage, leakage and component tolerance. Check R/C ranges in the TI LM555 datasheet.